ASM1542

Evaluation report, including

1. the "ESTIMATED" process technology,
2. die size,
3. the "ESTIMATED" number of poly and metal layers
4. Die photos with low resolution

Evaluation only, the work scope of high-resolution chip imaging area and circuit analysis is opened to discussion

• If you decide to perform a circuit analysis, we will provide a complete delivery. including BrigenOne, EDIF format schematics, and PDF file
• The project is still in the "evaluation" phase, and the work scope is open to discussing.
• The information we provide about this project will be somewhat uncertain, as we have not yet performed high-resolution wafer images of each layer.